Computing Community Consortium Blog

The goal of the Computing Community Consortium (CCC) is to catalyze the computing research community to debate longer range, more audacious research challenges; to build consensus around research visions; to evolve the most promising visions toward clearly defined initiatives; and to work with the funding organizations to move challenges and visions toward funding initiatives. The purpose of this blog is to provide a more immediate, online mechanism for dissemination of visioning concepts and community discussion/debate about them.

WATCH Talk- The CHERI Processor: Revisiting the Hardware-Software Interface for Security

June 29th, 2015 / in Announcements, NSF / by Helen Wright


The next WATCH talk, called The CHERI Processor: Revisiting the Hardware-Software Interface for Security is Monday July 6, 2015 from Noon-1pm EST.

The presenter is Dr Robert N.M. Watson. Robert is a University Lecturer in Systems, Security, and Architecture at the University of Cambridge Computer Laboratory. He has a strong interests in open-source software, is on the board of directors of the FreeBSD Foundation, and was founder of the FreeBSD Project. He earned his PhD from the University of Cambridge.



The last five years, supported by DARPA’s CRASH and MRC research programmes, SRI International and the University of Cambridge have been engaged in a project to revisit the fundamentals of CPU instruction-set design to improve security. The Capability Hardware Enhanced RISC Instructions design (CHERI) extends a conventional RISC Instruction-Set Architecture (ISA), processor, compiler, and operating system to support fine-grained, capability-based memory protection able to support both mitigation of memory-related vulnerabilities in C-language TCBs, and also extremely scalable software compartmentalization grounded in the principle of least privilege. Prototyped as a 64-bit RISC FPGA soft-core processor, and using the FreeBSD operating system, LLVM compiler suite, and open-source applications, we demonstrate strong and efficient mitigation of numerous current exploit techniques (e.g., buffer overflows, ROP attacks) and also in-address-space compartmentalization intended to mitigate future unknown classes of vulnerabilities and exploits. The CHERI model composes cleanly with current ISAs and software designs, and in particular, virtual memory memory based in Memory Management Units (MMUs) and C-language code, and offers an incremental adoption path for a stronger underlying protection model. This talk describes the architecture (published in a series of papers at ISCA, ASPLOS, and IEEE S&P), experimental approach grounded in hardware-software co-design,  and potential transition directions.

The talk will be held in Room 110 at the National Science Foundation in Arlington, VA. No RSVP is necessary, and no visitor badges are required. This talk will not be recorded or webcast, so please come in person if you can.

WATCH Talk- The CHERI Processor: Revisiting the Hardware-Software Interface for Security