Computing Community Consortium Blog

The goal of the Computing Community Consortium (CCC) is to catalyze the computing research community to debate longer range, more audacious research challenges; to build consensus around research visions; to evolve the most promising visions toward clearly defined initiatives; and to work with the funding organizations to move challenges and visions toward funding initiatives. The purpose of this blog is to provide a more immediate, online mechanism for dissemination of visioning concepts and community discussion/debate about them.

DARPA Seeking Unconventional Processors for ISR Data Analysis

August 29th, 2012 / in big science, research horizons, resources / by Erwin Gianchandani

Artist's concept: Through UPSIDE, sensor data is analyzed by an array of self-organizing devices; the array processes the data using inference, where elements of the image are automatically sorted based on similarities and dissimilarities; sensor data flows into the array and target identification and tracking is the output [image courtesy DARPA].Earlier this month, the Defense Advanced Research Projects Agency (DARPA) announced a new initiative that aims “to break the status quo of digital processing” by investigating new ways of “non-digital” computation that are “fundamentally different from current digital processors and the power and speed limitations associated with them.” Called Unconventional Processing of Signals for Intelligent Data Exploitation, or UPSIDE, the initiative specifically seeks “a new, ultra-low power processing method [that] may enable faster, mission-critical analysis of [intelligence, surveillance, and reconnaissance (ISR)] data.”

According to the DARPA announcement (after the jump):

Instead of traditional complementary metal-oxide-semiconductor (CMOS)-based electronics, UPSIDE envisions arrays of physics-based devices (nanoscale oscillators may be one example) performing the processing. These arrays would self-organize and adapt to inputs, meaning that they will not need to be programmed as digital processors are. Unlike traditional digital processors that operate by executing specific instructions to compute, it is envisioned that the UPSIDE arrays will rely on a higher level computational element based on probabilistic inference embedded within a digital system.


Probabilistic inference is the fundamental computational model for the UPSIDE program. An inference process uses energy minimization to determine a probability distribution to find the object that is the most likely interpretation of the sensor data. It can be implemented directly in approximate precision by traditional semiconductors as well as by new kinds of emerging devices.

DARPA program manager Dan Hammerstrom noted:

“Redefining the fundamental computation as inference could unlock processing speeds and power efficiency for visual data sets that are not currently possible. DARPA hopes that this type of technology will not only yield faster video and image analysis, but also lend itself to being scaled for increasingly smaller platforms.


“Leveraging the physics of devices to perform computations is not a new idea, but it is one that has never been fully realized. However, digital processors can no longer keep up with the requirements of the Defense mission. We are reaching a critical mass in terms of our understanding of the required algorithms, of probabilistic inference and its role in sensor data processing, and the sophistication of new kinds of emerging devices. At DARPA, we believe that the time has come to fund the development of systems based on these ideas and take computational capabilities to the next level.”

UPSIDE sets forth three specific tasks that interdisciplinary teams must tackle:

Task 1 forms the foundation for the program and involves the development of the computational model and the image processing application that will be used for demonstration and benchmarking.


Tasks 2 and 3 will build on the results of Task 1 to demonstrate the inference module implemented in mixed signal CMOS in Task 2 and with non-CMOS emerging nano-scale devices in Task 3.


The ability to successfully address all three tasks will require close collaboration within the proposer’s team and will be an important aspect of any successful UPSIDE effort.

To learn more, check out the official UPSIDE solicitation — and consider attending the UPSIDE Proposer’s Day workshop to be held on Sept. 10th at the DARPA Conference Center in Arlington, VA. And here’s a story in Wired about the new initiative.

(Contributed by Erwin Gianchandani, CCC Director)

DARPA Seeking Unconventional Processors for ISR Data Analysis