Computing Community Consortium Blog

The goal of the Computing Community Consortium (CCC) is to catalyze the computing research community to debate longer range, more audacious research challenges; to build consensus around research visions; to evolve the most promising visions toward clearly defined initiatives; and to work with the funding organizations to move challenges and visions toward funding initiatives. The purpose of this blog is to provide a more immediate, online mechanism for dissemination of visioning concepts and community discussion/debate about them.

NIST: $2.6 Million for Novel Semiconductor Research

March 23rd, 2012 / in research horizons, resources / by Erwin Gianchandani

NIST seeking proposals for industry-guided partnerships pursuing post-CMOS technology [image courtesy NIST].On Tuesday, the National Institute of Standards and Technology announced a solicitation for proposals that support long-term research in next-generation semiconductor technology, calling the work “critical to the future of the U.S. electronics industry.” Through the solicitation, NIST plans to issue one award of up to $2.6 million in Federal cost-shared funding (a minimum of 25 percent of a project’s budget must come from non-Federal sources) for the project’s first year, with the potential for continued funding for up to five years. Proposals are due by 5pm EDT on Monday, April 16th.

According to the solicitation:

One area where a clear long-term technological challenge resides is in the development of new semiconductor technology. Within 10 to 15 years the semiconductor industry will approach the limits of existing complementary metal oxide semiconductor (CMOS) technology, as atomicscale barriers limit the density of components that can be placed on a single chip. The semiconductor industry is well aware of this barrier and, through the International Technology Roadmap for Semiconductors (ITRS), has identified research on post-CMOS technologies as a high priority. In particular, the field of nanoscale electronics (often referred to as nanoelectronics) presents a number of promising research alternatives [more following the link].


NIST seeks to support a program that involves an industry-guided partnership that can include commercial, academic, non-profit, and/or government organizations to address the technical challenges highlighted in the ITRS roadmap. These challenges include the characterization and measurement techniques needed to develop novel nanoelectronic technologies that can demonstrate advantages over CMOS in power, density, performance, or cost. These technologies should include device, circuit, and architecture approaches in achieving the goals of low energy and high functionality. Non-conventional devices can include logic, memory, sensor, and analog components.


Industry is expected to play a guiding role in technical participation, advice, financial support, and other contributions to the partnership described in this section of the FFO. NIST will leverage Federal financial support with that of industry and other partners to increase the strategic investment in such a partnership by funding the recipient. Accordingly, the recipient is expected to be involved in an existing consortium, or create a new consortium, considered for purposes of this program to be an existing or new agreement, combination, or group formed to undertake an enterprise beyond the resources of any one member.


The consortium is expected to fund research at universities on post-CMOS technologies. Specifically, the consortium is expected to create a process for the review, selection, award, monitoring, and evaluation of research and development sub-awards to universities to be made by the consortium in support of addressing the technical challenges associated with nanoscale electronics and the development of non-conventional, low energy technologies which can outperform CMOS in the next decade. The recipient is expected to manage any funded consortium partners and university research supported by the Federal award via ordinary funding instruments, that is, sub-awards and/or contracts.


The technical scope of the consortium should explore fundamentally new approaches to low energy devices and technologies which can outperform traditional CMOS technologies. Topics of interest include:


  1. devices that utilize alternative state vectors for manipulating information such as collective effects, spin, magnetics, etc.;
  2. devices with higher computational density such as high logic efficiency, re-configurability, etc.;
  3. novel architectures that can exploit the non-conventional device behavior that manages information flow such as in non-Boolean and analog behavior;
  4. novel interconnect approaches; and
  5. non-equilibrium systems that have better noise immunity and low energy operation such as with phonon engineering.

Selection and award processing is expected to be completed in July, and the earliest start date for the awards is expected to be Oct. 1, 2012.

To learn more, check out the solicitation as well as the NIST press release announcing the funding opportunity.

(Contributed by Erwin Gianchandani, CCC Director)

NIST: $2.6 Million for Novel Semiconductor Research