Computing Community Consortium Blog

The goal of the Computing Community Consortium (CCC) is to catalyze the computing research community to debate longer range, more audacious research challenges; to build consensus around research visions; to evolve the most promising visions toward clearly defined initiatives; and to work with the funding organizations to move challenges and visions toward funding initiatives. The purpose of this blog is to provide a more immediate, online mechanism for dissemination of visioning concepts and community discussion/debate about them.

DARPA Announces Proposers Day for New PERFECT Program

January 31st, 2012 / in research horizons, resources / by Erwin Gianchandani

DARPA announces Proposers Day for new PERFECT program [image courtesy DARPA].The Defense Advanced Research Projects Agency’s (DARPA) Microsystems Technology Office (MTO) has announced a Proposers Day for a new program — Power Efficiency Revolution for Embedded Computing Technologies (PERFECT) — to introduce the research community to the PERFECT vision and goals, and to facilitate interaction and coordination among prospective PIs and technology developers. The Proposers Day will take place on February 15, 2012, in Arlington, VA.

The PERFECT program seeks to “provide the technologies and techniques to overcome the power efficiency barriers that currently constrain embedded computing systems capabilities and limit the potential of future embedded systems.” Importantly, a key component of this is resiliency, an area for which a recent CCC visioning activity on Cross-Layer Reliability led by Andre’ DeHon, Nick Carter, and Heather Quinn proffered a research roadmap.

From the Proposers Day announcement (following the link):

Computational capability is a primary constraint on the effectiveness of many, if not most, deployed military systems. Increasingly the ability to process sensor information on embedded systems is limited by the available on board computation. This is a result of the limited amount of electrical power available on the platforms and computational performance per watt. Examples show we need at least 50 GFLOPS/w, and requirements of at least 75 GFLOPS/w can be confidently anticipated. Current systems provide in the order of 1 GFLOPS/w and industry trends will provide power efficiencies that are well short of required performance.


The goal of the Power Efficiency Revolution For Embedded Computing Technologies (PERFECT) program is to provide a power efficiency of 75 GFLOPS/w for embedded computing systems. The PERFECT program will achieve this goal by taking a revolutionary approach to processing power efficiency. This approach includes near threshold voltage operation, massive heterogeneous processing concurrency, and novel architectural developments combined with techniques to effectively utilize the resulting concurrency and tolerate the resulting increased rate of soft errors. The PERFECT program will leverage anticipated industry fabrication geometry advances to 7 nm. Research and development will specifically address embedded systems processing power efficiencies and performance, and are not concerned with developments that focus on exascale processing issues. No operational hardware is to be built in this program, instead a simulation capability will be developed that will measure and demonstrate progress.


The PERFECT program will address five primary areas of technical research (Architecture, Concurrency, Resilience, Locality, and Algorithms), as well as two important support areas (Simulation, and Test and Verification). These research areas are necessarily not independent — for example, near‐threshold voltage architectures raise resilience issues — and therefore significant interaction among performers in these areas is expected.


The architecture element will address both hardware and software power efficiency innovation and development. Example areas anticipated for development include near threshold voltage operation, heterogeneous massive concurrent architectural approaches, novel hardware architectural approaches such as new memory hierarchies, application‐specialized cores, and data movement minimizing techniques. At the software level, the goal is to develop technologies and techniques that tolerate and exploit new hardware capabilities and overcome the associated limitations. This specifically will include addressing concurrency and reliability. The result of this research area will be the technologies to provide highly power efficient embedded processing systems.


The concurrency element will address the hardware and software to support high levels of concurrency — thousands to millions of concurrent execution streams. Hardware efforts in this area may include processing cores and data stores of varying capabilities and efficiencies and perhaps include automatically synthesized processing elements that are optimized for the embedded platform’s workload. Software efforts in this area may include language development or augmentation, compilers, and support software to specify and manage concurrent threads. Potential areas of investigation in this research area include: optimized critical DoD application kernel implementations, concurrency extraction (both top down and bottom up), dynamic execution, and heterogeneity management (both programmer directed and automated).


The resilience element will focus on the issue of soft errors. Such errors are expected to increase for near threshold voltage operation. Under this program, system resilience engineering will be moved onto the same quantifiable basis as performance engineering. This requires the ability to predict the resilience of designs so that quantitative tradeoffs are possible.


The locality element will focus on minimizing run‐time data communication by managing data location and availability. In particular, the memory hierarchy and the software to manage data are included.


Languages and language annotations that enable programmer control of data allocation as well a automatic control of data allocation will be investigated.


The algorithms program element will develop software techniques to minimize energy consumption. In addition, algorithmic approaches to enable the tolerance of hardware faults will be investigated, at both the kernel and the system levels.


Since no operational hardware is to be built in the PERFECT program, a simulation capability will be developed in order to measure and demonstrate progress. The simulation capability will be made available to technology developers.


The PERFECT program will have a The Test and Verification contractor (TAV). The TAV will define the benchmark applications that will be used to focus research and to assess progress; perform Feasibility Assessment Demonstrations (FAD) at the end of each Fiscal Year that will provide an assessment and demonstration of the feasibility of achieving the program goals; and provide Configuration Management that will retain and distribute released versions of hardware, software, and documents.

The Proposers Day — a free activity for the community — will be held at System Planning Corporation (SPC) in Arlington, VA, roughly from 7:30am to 4:30pm on February 15. Directions to this location can be found here.

As for the eventual program announcement:

DARPA intends to publish the PERFECT program BAA (DARPA‐BAA‐12‐24) prior to the scheduled Proposers Day. However, DARPA is not obligated to publish the BAA prior to conducting the Proposers Day or to publish an associated BAA at all. If and when published, the BAA will be made available — at a minimum — on the Federal Business Opportunities (FBO) website.

To learn more, check out the Proposers Day announcement. And for details about the cross-layer reliability vision, check out the the webpage for this CCC visioning activity.

(Contributed by Erwin Gianchandani, CCC Director)

DARPA Announces Proposers Day for New PERFECT Program