Just a week after announcing a Proposers Day for its new Power Efficiency Revolution for Embedded Computing Technologies (PERFECT) program, the Defense Advanced Research Projects Agency’s (DARPA) Microsystems Technology Office (MTO) has issued the official Broad Agency Announcement (BAA), soliciting proposals for innovative R&D in the area of embedded power efficient computing. As we’ve previously noted in this space, the goal for PERFECT is “to provide more effective embedded computing per watt of electrical power.”

According to the DARPA BAA:

The goal of the Power Efficiency Revolution For Embedded Computing Technologies (PERFECT) program is to provide a power efficiency of 75 GFLOPS/w for embedded computing systems [more following the link].

 

The PERFECT program will achieve this goal by taking a revolutionary approach to processing power efficiency. This approach includes near threshold voltage operation and massive heterogeneous processing concurrency, combined with techniques to effectively utilize the resulting concurrency and tolerate the resulting increased rate of soft errors. The PERFECT program will leverage and incorporate anticipated industry fabrication geometry advances to 7 nm. Since no operational hardware is to be built in this program, a simulation capability will be developed to measure and demonstrate progress.

 

This program specifically addresses embedded systems processing power efficiencies and performance, and is not concerned with developments that focus on exascale processing issues.

The PERFECT program is organized into 7 program elements:

…[Five] elements (Architecture, Concurrency, Resilience, Locality, and Algorithms) comprise the primary research efforts, and the remaining two (Simulation, and Test and Verification) are important support areas. These elements are necessarily not independent — for example, near‐threshold voltage architectures raise resilience issues — and therefore significant interaction among performers in these areas is expected. It should be noted that this program will not produce operational hardware, and therefore the simulation capability is essential, both to assessing progress and to determining whether the program goal of 75 GFLOPS/watt is achieved. Note also that through this BAA DARPA is soliciting proposals for only the first six program elements and not for the Test and Verification element.

And of these elements — resilience — concerns an area championed by André DeHon, Nick Carter, and Heather Quinn as part of a recent CCC visioning activity on Cross-Layer Reliability:

The Resilience Program Element is focused on the issue of soft errors. Such errors are expected to increase as transistor operating voltage is decreased toward the threshold voltage. Under this program, the art of system resilience design will be moved onto the same quantifiable basis on which performance architecture is currently done. This requires the ability to predict the resilience of designs so that quantitative tradeoffs are possible. This in turn requires accurate characterization of the resilience problem for plausible circuit/silicon designs. As noted above, the creation of models may precede building and evaluating test hardware.

According to the BAA, DARPA expects to issue multiple awards across three phases, the first of which will “primarily be initiating concepts and developing them as independent activities.”

To learn more, check out the full BAA or attend the upcoming Proposers Day on February 15.

(Contributed by Erwin Gianchandani, CCC Director)